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dc.contributor.author Verastegui, J.
dc.contributor.author Rojas, J.
dc.contributor.author Tupac, I.
dc.contributor.author Caceres, D.
dc.contributor.author Gonzales, L.
dc.date.accessioned 2021-07-09T13:27:42Z
dc.date.available 2021-07-09T13:27:42Z
dc.date.issued 2021-06
dc.identifier.uri http://hdl.handle.net/20.500.12816/4964
dc.description Poster presented at the 2021 CEDAR Virtual Workshop, June 20-25.
dc.description.abstract The latest data acquisition system running at the Jicamarca Radio Observatory for the main radar has been used for more than five years now. Although there are no major inconveniences on the performance there have been some problems with internal interferences which are usually unpredictable and related to the PCB design, the noise floor can be different between channels too. So there are some chances of improvement developing a new approach. We propose a new design based on a high speed JESD204B data interface; the digital signal processing and custom acquisition logic will be implemented inside an FPGA capable of managing the JESD204B high-speed interface. This will give us the flexibility of implementing digital blocks inside the FPGA to improve the performance of the receivers, we will gain scalability to perform on a much higher bandwidth and the PCB will be very much simplified which will reduce the manufacturing costs, design time, and development time. es_ES
dc.format application/pdf es_ES
dc.language.iso eng es_ES
dc.publisher Instituto Geofísico del Perú es_ES
dc.rights info:eu-repo/semantics/openAccess es_ES
dc.rights.uri https://creativecommons.org/licenses/by-nc-nd/4.0/ es_ES
dc.subject Acquisition System es_ES
dc.subject FPGA es_ES
dc.subject JESD204B es_ES
dc.subject PCB design es_ES
dc.subject HDL design es_ES
dc.title JRO digital receiver modernization using ADCs with high-speed JESD204B data interface and FPGAs es_ES
dc.type info:eu-repo/semantics/conferenceObject es_ES
dc.subject.ocde https://purl.org/pe-repo/ocde/ford#1.05.01 es_ES

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