Digital receiver modernization using FPGA and JESD204B interface for SDR applications

Simple item page
dc.contributor.authorVerástegui, Joaquín
dc.contributor.authorRojas, John
dc.contributor.authorTupac, Isaac
dc.contributor.authorGonzales, Luis
dc.date.accessioned2023-04-03T22:26:00Z
dc.date.available2023-04-03T22:26:00Z
dc.date.issued2023
dc.description.abstractThe latest data acquisition system running at the Jicamarca Radio Observatory (JRO) for the main radar has been used for more than seven years now. Although there are no major inconveniences on the performance, there have been some problems with internal interference which are related to the PCB design that uses old discrete components. A new design is proposed for the digital receivers, giving it more lifetime and flexibility for future modifications. The JESD204B protocol is ideal for radar applications, a JESD204B ADC together with an FPGA was proposed for the new design, making it capable of a wider bandwidth which could adapt the system to an SDR device in the future with the proper software. This paper will present the new PCB design, the IP cores implemented for the FPGA and some preliminary tests with development boards.es_ES
dc.formatapplication/pdfes_ES
dc.identifier.citationVerástegui, J., Rojas, J., Tupac, I., & Gonzales, L. (2023). Digital receiver modernization using FPGA and JESD204B interface for SDR applications. Paper presented at the ==$2023 United States National Committee of URSI National Radio Science Meeting, USNC-URSI NRSM 2023 - Proceedings,$==321-322. https://doi.org/10.23919/USNC-URSINRSM57470.2023.10043159es_ES
dc.identifier.doihttps://doi.org/10.23919/USNC-URSINRSM57470.2023.10043159es_ES
dc.identifier.govdocindex-oti2018
dc.identifier.urihttp://hdl.handle.net/20.500.12816/5373
dc.language.isoenges_ES
dc.publisherIEEE, Institute of Electrical and Electronics Engineerses_ES
dc.rightsinfo:eu-repo/semantics/closedAccesses_ES
dc.subjectProtocolses_ES
dc.subjectObservatorieses_ES
dc.subjectData acquisitiones_ES
dc.subjectReceiverses_ES
dc.subjectInterferencees_ES
dc.subjectBandwidthes_ES
dc.subjectSoftwarees_ES
dc.subject.ocdehttps://purl.org/pe-repo/ocde/ford#1.05.01es_ES
dc.titleDigital receiver modernization using FPGA and JESD204B interface for SDR applicationses_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES

Files

Original bundle
Now showing 1 - 1 of 1
No Thumbnail Available
Name:
Verastegui_et_al_2023_USNC_URSI_NRSM.pdf
Size:
2.65 MB
Format:
Adobe Portable Document Format
Description:
Download
License bundle
Now showing 1 - 1 of 1
No Thumbnail Available
Name:
license.txt
Size:
1.71 KB
Format:
Item-specific license agreed upon to submission
Description:
Download

Collections

Artículos Científicos