Synchronous programmable sequencer (SPS)

dc.contributor.authorTobaja, E.
dc.contributor.authorWoodman Pollitt, Ronald Francisco
dc.contributor.authorHaseltine, D.
dc.date.accessioned2018-07-05T11:45:17Z
dc.date.available2018-07-05T11:45:17Z
dc.date.issued1978-09
dc.descriptionEn: Arecibo Observatory, Electronics Departament, Technical Report 7801, September 1978, 6 p.es_ES
dc.description.abstractThe purpose of this document is lo provide the user, the maintenance engineer, and the system programmer with the necessary information for its maintenance and use. The document provides more information than would normally be required by the average experimental user. The latter may want to limit himself to reading the following "Short. Description" and taking a quick look at the rest of the document. The SPS has been implemented on a Harris universal interface wire wrap card. This card, bought from Harris, contains all the interface element’s needed to communicate to and from the computer. They are mounted in wire wrap IC sockets and wired lo their respective pins in the channel communications cable connectors. Since the card also contains a number of 16 and 14 pins wire wrap IC sockets, the SPS logic is implemented here by populating these sockets and interconnecting them.es_ES
dc.description.sponsorshipArecibo Observatoryes_ES
dc.formatapplication/pdfes_ES
dc.identifier.urihttp://hdl.handle.net/20.500.12816/1707
dc.language.isoenges_ES
dc.publisherInstituto Geofísico del Perúes_ES
dc.rightsinfo:eu-repo/semantics/restrictedAccesses_ES
dc.subjectComputer systemses_ES
dc.subjectComputer softwarees_ES
dc.subjectMaintenance and repaires_ES
dc.subjectObservatorieses_ES
dc.subjectElectronic systemses_ES
dc.subject.ocdehttp://purl.org/pe-repo/ocde/ford#1.05.01es_ES
dc.titleSynchronous programmable sequencer (SPS)es_ES
dc.typeinfo:eu-repo/semantics/technicalDocumentationes_ES

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