Mostrar el registro sencillo del ítem Rojas, John Verástegui, Joaquin Milla, Marco 2018-09-25T17:46:17Z 2018-09-25T17:46:17Z 2018-01
dc.identifier.citation Rojas, J., Verástegui, J., & Milla, M. (2018). Design and implementation of a high speed interface system over Gigabit Ethernet based on FPGA for use on radar acquisition systems.==$2017 Electronic Congress (E-CON UNI),$==22-24 Nov. 2017, Lima, Peru. es_ES
dc.identifier.govdoc index-oti2018
dc.description.abstract The Jicamarca Radio Observatory (JRO) is part of the Western Hemisphere chain of Incoherent Scatter Radar (ISR) observatories which extends from Lima, Peru to S0ndre Str0mfjord, Greenland. The equatorial ionosphere is studied only by JRO in the world. The Observatory is a facility of the Instituto Geofísico del PerU operated with support from the US National Science Foundation Cooperative Agreements through Cornell University. One of the main radar components is JARS (Jicamarca Acquisition Radar System), which functionality is based on CPLDs (Complex Programmable Logic Device) to configure the system and transfer the data from the digital receivers to the acquisition computer over a proprietary interface NI PCIe-6537. However due to some limitations as its high cost, driver updates dependency and the data transfer speed, it was necessary to replace this interface with the design and implementation of a high-speed hardware, embedded on FPGA devices, to transmit the data through the LVDS interface to a double buffering stage, and forward these as packets on the standard Gigabit Ethernet, based on the IEEE 802.3 protocol and using the UDP protocol. In this way, this development will allow to update the hardware of the current JARS to get a low cost portable system and to work with the required bandwidth. A prototype of this system was developed on the JRO and also a customized software was written, based on UDP socket and multiple threads of execution. es_ES
dc.format application/pdf es_ES
dc.language.iso eng es_ES
dc.publisher Institute of Electrical and Electronics Engineers es_ES
dc.relation.ispartof urn:isbn:9781538622780
dc.rights info:eu-repo/semantics/restrictedAccess es_ES
dc.subject FPGA es_ES
dc.subject LVDS es_ES
dc.subject Double buffering es_ES
dc.subject Gigabit Ethernet es_ES
dc.subject UDP es_ES
dc.subject Threads of execution es_ES
dc.title Design and implementation of a high speed interface system over Gigabit Ethernet based on FPGA for use on radar acquisition systems es_ES
dc.type info:eu-repo/semantics/conferenceObject es_ES
dc.subject.ocde es_ES
dc.identifier.doi es_ES




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