Browsing by Author "Verastegui, Joaquin"
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Item Restricted Design and development of a low-cost wireless network using IoT technologies for a mudslides monitoring system(IEEE, Institute of Electrical and Electronics Engineers, 2021) Meléndez Coveñas, Frank Enrique; Palomares, Ricardo; Milla, Marco; Verastegui, Joaquin; Cornejo, JoséThe city of Lima - Peru is affected periodically by mudslides and floods caused by torrential rains near Lima's mountain region. The Jicamarca ravine is especially affected by this phenomenon and is also critical to the population because of its proximity to SEDAPAL's water treatment plant that provides drinking water service to approximately 80% of homes in Lima city. In addition to this, there are a lot of houses located near the riversides affected by the mudslides that could be affected by the overflows. This paper describes the implementation of a low-cost wireless sensor network based on Internet of Things (IoT) technologies designed for monitoring mudslides events made by the association of the Professional School of Electronic Engineering and Telecommunications of the Universidad Nacional Tecnológica de Lima Sur and the Radio Observatorio de Jicamarca, research facility of the Instituto Geofísico del Perú. The network consists of various monitoring stations based on the ESP32 microcontroller and it takes advantage of the Long-Range mode of this device. The radio links created have a range of more than 1 km and all of them are connected to one access point which has a connection to the internet using the IoT technology of the cellular mobile network. The access point sends data to a server in the cloud allowing access to sensors remotely without putting people's lives at risk. This project is part of a program of the Instituto Geofísico del Perú with the goal of implementing a National Mudslide Monitoring Center.Item Restricted Design of a Programmable Radar Controller ASIC on VHDL for a Modular Radar System(IEEE, Institute of Electrical and Electronics Engineers, 2021) Verastegui, Joaquin; Manay, Ivan; Pacheco, Edgardo E.; Milla, MarcoThe Jicamarca Radio Observatory (JRO), funded by the USA National Science Foundation (NSF), operates several radars for different applications, from the main radar, an incoherent scatter radar used mainly for ionospheric activity observations, to ionosondes and wind profilers. Most of these radars use a centralized modular control system that commands all the radar sequences that require the radar modules, these tasks and sequences are controlled by pulsed digital signals. The device responsible for this operation is called the Radar Controller. A large number of customized Radar Controller versions were developed and built at JRO for decades, since the utilization of its first acquisition system. The current version of the Radar Controller is based on an RTL design written on VHDL language that implements a custom arbitrary waveform generator connected to an SRAM memory that stores all the data a given waveform needs. The Radar Controller uses a register based architecture to communicate between blocks internally. In JRO we use a Spartan 6 FPGA and it is controlled by a Tiva C microcontroller board which has an Ethernet port. A Restful API has been implemented on the microcontroller for user configuration. This paper will cover the VHDL RTL design of the current version of the Radar Controller core.